1. Field of the Invention
The present invention relates to an equalizer and an equalization method and, more particularly, to an equalizer and an equalization method for transmitting data at high speed.
2. Description of the Related Art
The IEEE STD 802.3.ba standard for a high speed Ethernet backplane stipulates that a 10G Ethernet transmission equalizer be employed in a channel transmission unit and a bit error rate (BER) performance of 10 to 12 or higher be provided when a 1-meter backplane PCB pattern is passed through. Thus, the design of an equalizer for a high speed Ethernet backplane is a critical factor in designing a high speed Ethernet backplane.
FIG. 1 illustrates an overall structure of the existing decision feedback equalizer.
With reference to FIG. 1, the existing decision feedback equalizer 200 includes a sampling timing extraction unit 210, a sampler 220, a feedforward filter 230, a subtractor 240, a slicer 250, a feedback filter 260, and an adapter 270.
The operation of the decision feedback equalizer 200 will now be described.
In a non-equilibrium state, the sampling timing extraction unit 210 acquires a sampling timing (T) by using a reception signal XA(t), and after compensation is made through the decision feedback equalizer 200, the sampling timing extraction unit 210 determines a sampling timing by using an output signal Yo(nT).
The sampler 220 samples the analog input signal XA(t) according to the sampling timing (T) to generate a digital input signal XO(nT). Namely, the sampler 220 serves to digitalize the input signal. The carrier frequency is high in high speed data communication, so the sampling frequency accordingly needs to become high in order to avoid aliasing.
The feedforward filter 230 and the feedback filter 260 of the decision feedback equalizer 200 are elements for removing a precursor inter-symbol interference (ISI) and a post-cursor ISI, respectively.
The subtractor 240 subtracts a digital feedback signal ZO(nT), acquired from a signal before one period, from the digital input signal XO(nT) which has passed through the feedforward filter 230. When the feedback signal is subtracted, the post-cursor ISI is canceled.
When the subtracted signal is sliced by the slicer 250, a digital equalization signal Dn(nT) is obtained.
The feedback filter 260 delays and weights the digital equalization signal Dn(nT) to generate a feedback signal.
The adapter 270 calculates a tap coefficient to be used when the feedback filter 260 weights each delayed digital equalization signal and delivers it to the feedback filter 260. In this case, the adapter 270 must calculate the tap coefficient such that it can sufficiently compensate for a channel. Thus, a tap coefficient calculation method of the adapter 270 may differ, depending on a channel situation or a field of application for the equalizer. Also, the adapter 270 may not be used according to a channel situation.
When a channel situation is not fixed or poor, an adaptive adapter for updating a tap coefficient according to an environment may be used.
In general, on-time sampling is performed in an area where eyes are widest. In this respect, when crosstalk induced jitter (CIJ), signal attenuation, and the like, exist in a channel, the size of eyes are relatively closed, making it difficult to expect maximum eye opening at on-time.
Also, in a case in which a high speed backplane distributedly delivers 400 Gb/s of data through multiple channels, each having 10 Gb/s bandwidth, a reflection loss, crosstalk, jitter, and the like, affect the respective adjacent channels at transmission and reception backplane connector parts. Thus, in order to prevent severe degradation of reception performance due to increased loss and noise, the channels need to be sufficiently compensated for.